1. Field of the Invention
The field of the invention relates to the field of data storage and in particular, to the storage and access of data in semiconductor memories.
2. Description of the Prior Art
With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input data value must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops.
SRAM bit cells are generally designed to be small and can conventionally be built from 6 transistors. However, dual port cells are also known that are built from 8 transistors. These are conventionally used in conjunction with two word lines and two bit lines, and have two sets of access transistors, one for connecting a first word line and set of bit lines to the feedback loop and the other for connecting a second word line and set of bit lines to the feedback loop. These dual port bit cells allow two cells to be accessed in the same cycle by the use of these different ports and access lines. Clearly care must be taken not to try to read and write to the same cell in the same cycle.
When accessing a bit cell in such memories there is generally a precharge phase during which both bit lines are precharged and then there is an evaluation phase where access transistors are turned on and either the value stored in the cell is transferred to the bit lines, or a value to be written to the cell is transferred to the bit lines and is then transferred to the cell via the access transistors. In a write the data value is placed on the bit lines by driving the complementary bit lines to the required voltage the access transistors are turned on and the feedback loop is connected to the bit lines and the data value on the bit lines is stored in the feedback loop. When reading from a cell both bit lines are pre-charged and the side of the cell storing a 0 will pull down the bit line when it is connected to it and this change in voltage level can be detected to determine on which side of the feedback loop the 0 is stored. However, the difference in voltage levels between the precharged bit line and the 0 may result in the node storing a 0 being pulled up towards 1 resulting in instability in the bit cell and the bit cell flipping value. This is called read disturb and can happen to a cell during a read to a cell or during a write to another cell on the same word line. In the latter case the word line is activated to access the cell being written to, which affects other cells connected to the word line.
As dimensions scale down the variations in device properties due to random dopant fluctuations, line edge roughness etc. increase drastically thereby causing an increase in the rate of read disturbs as well as reduced write margins, with smaller scale geometries.
Thus, designing a robust SRAM where cells can be read (without read disturb) and written to across all operational voltage ranges turns out to be difficult. Reducing the voltage at which the SRAM cells can be read and written to successfully is not easy and in particular as the voltage scales down it becomes increasingly difficult to write to the cells. Write assist mechanisms that increase the voltage on the word line during a write to improve access are known but such techniques have the disadvantage of increasing the probability of a read disturb to a cell on the same row as the cell being accessed and require the provision of an additional higher voltage level.
It would be desirable to be able to reduce write failures of a semiconductor memory without unduly increasing the read failures.